With increasing frequency devices work, signal integrity issues faced by high-speed PCB design becomes a bottleneck of traditional designs, engineers face a growing challenge in the design of a complete solution. Although related to the high-speed simulation tools and interconnect design tools can help designers to solve some problems, but high-speed PCB design also need in-depth exchange of experience between the accumulation and the industry.
Listed below are some of the issues of wide public concern.
The impact on signal integrity wiring topology
When the signal transmission in high-speed PCB board along the transmission line may cause signal integrity problems. STMicroelectronics friends tongyang Q: For a group bus (address, data, commands) to drive up to four or five devices (FLASH, SDRAM, etc.), the PCB layout when a bus in order to reach the various devices, such as the first connected to SDRAM, FLASH ...... or bus and then was distributed star, which is separated from somewhere, are connected to each device. These two methods on signal integrity, which is better?
In this regard, Li Po Lung noted that the effects on signal integrity cabling topology, mainly reflecting on each node of the signal arrival time is inconsistent, the arrival time of the reflected signal is also a node of a mismatch, resulting in deterioration of signal quality. In general, the star topology, can be controlled by several branches of the same length, so that the signal transmission and reflection delay consistent, achieve better signal quality. Between the use of topology, topology nodes to take into account the signal case, actually works and wiring difficulty. Different Buffer, the signal reflections also inconsistent, so the star topology is not well solve the data address bus is connected to FLASH and SDRAM delay, and thus can not ensure the quality of the signal; on the other hand, high-speed signal is generally in communication between the DSP and SDRAM, FLASH loading rate is not high, so high-speed simulation Just make sure that the actual speed signal waveforms at the nodes to work effectively, without having to focus on the waveform FLASH; star topology is a daisy chain topology speaking, the wiring is difficult, especially in large amounts of data are used when the address signal a star topology.
The impact of high-speed signal pads
In the PCB, from design point of view of a through-hole is mainly composed of two parts: the middle of the drilling and drilling pads around. There engineer named fulonm ask guests to pad the impact of high-speed signals, which, Li Po Lung said: pads for high-speed signal affected, the impact effect similar device packaging of the device. Detailed analysis, after a signal from inside IC, after bonding line, pin package housing, pads, solder arrival transmission line, all the joints of the process will affect the quality of the signal. However, the actual analysis, it is difficult to give the pad, solder pins plus specific parameters. Therefore, the general parameters of the model with the IBIS package outlines all of them, of course, such an analysis at a lower frequency can receive, but for higher-frequency signal more accurate simulation is not enough accurate. A trend now is to use VI, VT curve characteristics of IBIS description Buffer parameters describe the package with the SPICE model.